Mapping Applications to Coarse-Grain Reconfigurable Architectures

Coarse-grained reconfigurable architectures (CGRAs) are capable of achieving both goals of high performance and flexibility. CGRAs not only improve performance by exploiting the features of repetitive computations, but also can adapt to diverse computations by dynamically changing configurations of an array of its internal processing elements (PEs) and their interconnections. Many CGRAs have been developed recently as programmable coprocessors, minimizing the overhead of the central processor in many computation-intensive applications. They act as co-processors for accelerating computation-intensive portions of embedded system applications. System designers are attracted to CGRAs because they bridge the gap between Application Specific Integrated Circuits (ASICs) and microprocessors by providing the high performance of ASICs with flexibility of reconfiguration of fine-grained FPGAs. Some of the application areas of these architectures are image processing, DSP, encryption, pattern recognition, and other multimedia applications. This paper surveys the methods of compiling applications to coarse-grained reconfigurable architectures.